16 pin dil 3 bit programmable ecl delay lines package schematic *these two values are inter-dependent. recommended operating conditions parameter min max unit v ee supply voltage (negative) 4.94 5.46 v v cc circuit ground (pins 1 and 16) 0 0 v v ih high level input voltage -980 -810 mv v iht high level input threshold voltage -1105 mv v il low level input voltage -1850 -1630 mv v ilt low level input threshold voltage -1475 mv p w* pulse width of total delay 40 % d* duty cycle 40 % t a operating free-air temperature -30 +80 ? dc electrical characterstics (v cci = v cc2 = grd, v ee = 5.2v ?.01v output loading with 50 ohms to -2.0v?.01v) test parameter conditions min max unit v oh high level ouput voltage v il = min -960 mv v oht high level output -980 mv threshold voltage v olt low level ouptut -1630 mv threshold voltage v ol low level output voltage v ih = max -1650 i ih high level input current v ih = max 15 ma i il low level input current v il = min 0.5 ma -i ee v ee supply current 75 ma input pulse test conditions @ 25?c v in pulse input voltage -1.0v (-0.75 to - 1.75v) p in pulse width of total delay 3 x max delay t ri pulse rise time 2 ns p rr pulse repetition rate 10 x td v ee supply voltage -5.2v delays and tolerances (in ns) delay/step part number step delay tolerance (ref. inherent delay) truth table (programming pins = cba) 000 001 010 011 100 101 110 111 ep9450-1 ep9450-2 ep9450-3 ep9450-4 ep9450-5 ep9450-6 ep9450-7 ep9450-8 ep9450-9 ep9450-10 ep9450-15 ep9450-20 ep9450-25 ep9450-30 ep9450-35 ep9450-40 ep9450-45 EP9450-50 3.0 ?.3 3.0 ?.3 3.0 ?.3 3.0 ?.3 3.0 ?.3 3.0 ?.3 3.0 ?.3 3.0 ?.3 3.0 ?.3 3.0 ?.3 3.0 ?.3 3.0 ?.3 3.0 ?.3 3.0 ?.3 3.0 ?.3 3.0 ?.3 3.0 ?.3 3.0 ?.3 10 17 24 31 38 45 52 59 66 73 108 143 178 213 248 283 318 353 1 ?.3 2 ?.4 3 ?.5 4 ?.5 5 ?.5 6 ?.6 7 ?.7 8 ?.8 9 ?.9 10 ?1.0 15 ?1.5 20 ?2.0 25 ?2.0 30 ?2.0 35 ?2.0 40 ?2.5 45 ?2.5 50 ?2.5 ?.4 ns or ?% ?.6 ns or ?% ?.8 ns or ?% ?.0 ns or ?% ?.0 ns or ?% ?.0 ns or ?% ?.0 ns or ?% ?.0 ns or ?% ?.0 ns or ?% ?.0 ns or ?% ?.0 ns or ?% ?.0 ns or ?% ?.0 ns or ?% ?.0 ns or ?% ?.0 ns or ?% ?.0 ns or ?% ?.0 ns or ?% ?.0 ns or ?% 3 4 5 6 7 8 9 10 3 5 7 9 11 13 15 17 3 6 9 12 15 18 21 24 3 7 11 15 19 23 27 31 3 8 13 18 23 28 33 38 3 9 15 21 27 33 39 45 3 10 17 24 31 38 45 52 3 11 19 27 35 43 51 59 3 12 21 30 39 48 57 66 3 13 23 33 43 53 63 73 3 18 33 48 63 78 93 108 3 23 43 63 83 103 123 143 3 28 53 78 103 128 153 178 3 33 63 93 123 153 183 213 3 38 73 108 143 178 213 248 3 43 83 123 163 203 243 283 3 48 93 138 183 228 273 318 3 53 103 153 203 253 303 353 delay times referenced from input to leading edges at 25?, 5.0v. max imum (nom) delay minimum (inheren t) delay dsd83xx 8/25/94 qaf-cso1 rev. b 8/25/94 unless otherwise noted dimensions in inches tolerances: fractional = ?1/32 .xx = ?.030 .xxx = ?.010 16799 schoenborn st. north hills, ca 91343 tel: (818) 892-0761 fax: (818) 894-5791 e l e c t r o n i c s i n c . 1 2 6 7 8 9 10 15 16 vcc output b c vee a input e vcc programmable delay line white dot pin 1 .275 max. .020 .040 .700 .100 .800 max. .300 pca ep9450-1 date code .400 max. .010 x .018 typ. .130 typ.
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